Data receivers, such as DRAM data receivers, should be extremely precise in order to discern bits at high frequencies. As frequencies increase, data receivers are more sensitive to input referred offset caused by device mismatch. As data is provided to a data receiver, the inputs may be discerned incorrectly causing errors in the system. For example, if the offset between the data provider and the data receiver is high, a bit with a high value may be interpreted as a low value, causing an error. Correction circuits may be utilized to reduce the effects of device mismatch offset. An important part of an offset correction circuit is the majority detector. The majority detector is utilized to help determine the amount of offset that may be needed to reduce or eliminate device mismatch.
To calibrate the system for offset correction one input of a differential data receiver is held at or near a calibration voltage. A variable voltage relative to the calibration voltage is provided to the second input of the differential data receiver. A clock signal is also input into the data receiver. For each active clock edge, a digital output is provided to the majority detector. Assuming the calibration voltage is applied to the non-inverting input of the differential data receiver, the output will be a series of ones if the calibration voltage is sensed to be significantly higher than the variable voltage plus the offset voltage. The output will be a series of zeros if the calibration voltage is sensed to be significantly lower than the variable voltage plus the offset voltage. Mostly due to thermal noise, when the calibration voltage is equal to or approximately equal to the variable voltage, plus the offset voltage, a random series of ones and zeros will be present at the data receiver output.
To calibrate the system, the variable voltage is raised or lowered until a transition is achieved, such as a transition from a greater number of ones than zeros, to a greater number of zeros than ones. For each given variable voltage the system counts the number of “one” bits received over a sensing period. For example, the system may begin with a significantly higher variable voltage than the calibration voltage. In that case the majority detector concludes the number of zeros in the experiment will exceed the number of ones. The system may then incrementally lower the variable voltage after each experiment generating the same conclusion (i.e. a majority of zeros). When the number of zeros detected becomes equal to or less than the number of ones detected within one experiment, as concluded by the majority detector, the variable voltage plus the offset voltage will be equal to or approximately equal to the calibration voltage. Because the variable voltage is relative to the calibration voltage the offset voltage can be determined as the difference of the two, its value stored and used in normal operation.